Projekte
projekt1
BlueGrey
calm
Elegant
Català-Valencià – Catalan
中文 – Chinese (Simplified)
中文 – Chinese (Traditional)
Česky – Czech
Dansk – Danish
Nederlands – Dutch
English – English
Suomi – Finnish
Français – French
Deutsch – German
עברית – Hebrew
हिंदी – Hindi
Magyar – Hungarian
Bahasa Indonesia – Indonesian
Italiano – Italian
日本語 – Japanese
한국어 – Korean
Македонски – Macedonian
मराठी – Marathi
Norsk – Norwegian
Polski – Polish
Português – Portuguese
Português – Portuguese (Brazil)
Русский – Russian
Slovenčina – Slovak
Slovenščina – Slovenian
Español – Spanish
Svenska – Swedish
Türkçe – Turkish
Українська – Ukrainian
Oëzbekcha – Uzbek
Subversion Repositories
Projekte
(root)
/
DesignRules/
– Rev 8002
Rev
Search
Rev 7892
|
Last modification
|
Compare with Previous
|
View Log
|
RSS feed
Last modification
Rev 7999 2026-01-27 10:20:59
Author:
eiserbeck
Log message:
alles gespeichert
Path
Last modification
Log
RSS
JLC/
7999
8 d 3 h
eiserbeck
Log
RSS
2012_08_13_Altium DRC fuer PCB-POOL(R).pdf
2620
4923 d 7 h
eiserbeck
Log
RSS
20230929_JLCPCB_BOM.xls
7023
821 d 1 h
eiserbeck
Log
RSS
BestückungsDruck.OutJob
7762
299 d 7 h
eiserbeck
Log
RSS
BOM.OutJob
7999
8 d 3 h
eiserbeck
Log
RSS
Farnell_BOM.OutJob
7892
100 d 4 h
eiserbeck
Log
RSS
M10V_bestücker.OutJob
7701
372 d 1 h
eiserbeck
Log
RSS
OdbZollner_BOM .OutJob
7411
580 d 2 h
eiserbeck
Log
RSS
PCBPool_Altium20_Standard.RUL
5672
1883 d 1 h
eiserbeck
Log
RSS
PCBPool_Altium_Minimal.RUL
2728
4761 d 6 h
kaessler
Log
RSS
PCBPool_Altium_Standard.RUL
5498
2002 d 2 h
thieme
Log
RSS
PCBPool_Altium_Standard_ME.RUL
7701
372 d 1 h
eiserbeck
Log
RSS
Voltera.OutJob
7023
821 d 1 h
eiserbeck
Log
RSS
WegST.txt
7242
679 d 4 h
eiserbeck
Log
RSS
WegSTr.OutJob
7792
197 d 0 h
eiserbeck
Log
RSS
WegST_FlatCAM.lnk
7242
679 d 4 h
eiserbeck
Log
RSS
Würth_ME.RUL
2349
5186 d 5 h
eiserbeck
Log
RSS
Zollner_BOM.xls
7023
821 d 1 h
eiserbeck
Log
RSS